Embedded System - Beaglebone

 

 

 

 

Memory Map and Registers

 

Our brain is functionally divided into multiple regions and each and every parts of our body is controlled by a specific region of a brain. It means each and every parts of our body is somehow connected to some specific parts of a brain. If you stimulate a specific parts of the brain that is connected to a specific body part, that body parts would response in specific way. For example, if you stimulate the brain parts that is connected to a mustle in your arm, the mustle would twitch.

Likewise, Hardware parts on Computer/Microprocessor board and memory on the board is in very similar relation between our brain and body parts. It means, each and every parts of the hardware is somewhow connected to a some part in the memory. If you write some value in a specific parts of the memory, it is reflected as a specific action of a hardware. A most common hardware in Microsprocessor board would be various I/O pins and communication ports. All of these pins and ports are connected to a specific parts of the memory. In most case, which parts of the memory is connected to which part of the hardware is determined by the CPU/Microcontroller type and the operating system. You can create a table or diagram showing each functional blocks of the memory. This table or diagram is called Memory Map.

If you understand the memory map of a specific CPU/Microprocessor, you can directly controls a specific hardware by writing some value directly into a specific memory location or you can figure out the status of a specific hardware by reading the value of a specific memory portion (address).

If you are a programmer running on a modern operating system, there wouldn't be many cases where you need to read/write to/from the memory because in modern operating system you just send some high level command and operating system is doing all the necessary details to control the hardware and in most case you are not even allowed to directly read/write on memory. However, in Microprocessor (Embedded) application there are still many cases where it is better to control the hardware by direct read/write on memory. So it is still important to understand the details of the memory map and every microprocessor manufacture publish the memory map in their technical reference. However, if you are new to this area, the biggest problem is to understand the document itself. It would just like a long tables showing just a bunch of magic numbers (or looks like garbage).

In this page, I will try to show you how to interpret the memory map of Beaglebone Microprocessor (AM335x Sitara™ Processors).

 

 

GPIO Memory Map and Registers

 

 

 

 

 

 

GPIO Pin Number on Board and Memory Map

 

GPIO on Board

GPIO Bank on Momory

Bit #

Header on Board

Address

2

0

2

P9_22

 

3

0

3

P9_21

 

4

0

4

P9_18

 

5

0

5

P9_17

 

7

0

7

P9_42A

 

8

0

8

P8_35

 

9

0

9

P8_33

 

10

0

10

P8_31

 

11

0

11

P8_32

 

12

0

12

P9_20

 

13

0

13

P9_19

 

14

0

14

P9_26

 

15

0

15

P9_24

 

20

0

20

P9_41A

 

22

0

22

P8_19

 

23

0

23

P8_13

 

26

0

26

P8_14

 

27

0

27

P8_17

 

30

0

30

P9_11

 

31

0

31

P9_13

 

32

1

0

P8_25

 

33

1

1

P8_24

 

34

1

2

P8_05

 

35

1

3

P8_06

 

36

1

4

P8_23

 

37

1

5

P8_22

 

38

1

6

P8_03

 

39

1

7

P8_04

 

44

1

12

P8_12

 

45

1

13

P8_11

 

46

1

14

P8_16

 

47

1

15

P8_15

 

48

1

16

P9_15

 

49

1

17

P9_23

 

50

1

18

P9_14

 

51

1

19

P9_16

 

60

1

28

P9_12

 

61

1

29

P8_26

 

62

1

30

P8_21

 

63

1

31

P8_20

 

65

2

1

P8_18

 

66

2

2

P8_07

 

67

2

3

P8_08

 

68

2

4

P8_10

 

69

2

5

P8_09

 

70

2

6

P8_45

 

71

2

7

P8_46

 

72

2

8

P8_43

 

73

2

9

P8_44

 

74

2

10

P8_41

 

75

2

11

P8_42

 

76

2

12

P8_39

 

77

2

13

P8_43

 

78

2

14

P8_37

 

79

2

15

P8_38

 

80

2

16

P8_36

 

81

2

17

P8_34

 

86

2

22

P8_27

 

87

2

23

P8_29

 

88

2

24

P8_28

 

89

2

25

P8_30

 

110

3

14

P9_31

 

111

3

15

P9_29

 

112

3

16

P9_30

 

113

3

17

P9_28

 

114

3

18

P9_42B

 

115

3

19

P9_27

 

116

3

20

P9_41B

 

117

3

21

P9_25

 

 

 

UART Memory Map and Registers

 

 

 

< Table 2-2. L4_WKUP Peripheral Memory Map >

 

< Table 4-199. PRU_ICSS_UART Registers >

 

 

Reference :

[1] AM335x Sitara™ Processors Technical Reference Manual  

[2] Exploring Beaglebone - Chap 6