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makefile
As you know, in order to execute the program written in C, we need to do compilation and link to convert the c source code to an executable binary file. This compilation and link process would not be a big issue if you are handling a small number of c files and h files, but the process would go more and more complicated as the number of those files increases and you need to use more complicated compilation / link options. Repeating those compilation and link process over and over can be an annoying process. makefile is a kind of batch file (similar to shell program) that execute the predefined compilation/link procedure.
If you have tried to use any large scale programs (like those open source programs you can get from internet or github), you would noticed that most of the program source codes are provided with its own makefile and understanding the contents of the makefiles are not an easy task.
This note is intended to help you with understanding the contents of makefile provided with those programs and help you with creating makefiles for your own program.
Compile without makefile
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hello.c
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hello.h
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#include "hello.h"
int main(void)
{
print_hello();
return 1;
}
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#include <stdio.h>
void print_hello(void)
{
printf("Hello World \n");
}
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Simplest makefile
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hello.c
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hello.h
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#include "hello.h"
int main(void)
{
print_hello();
return 1;
}
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#include <stdio.h>
void print_hello(void)
{
printf("Hello World \n");
}
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Example 01 >
| makefile |
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hello:
gcc hello.c -o hello
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Example 02 >
| makefile |
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hello:
gcc -o hello hello.c
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Example 03 >
| makefile |
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hello: hello.c
gcc -o hello hello.c
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Example 04 >
| makefile |
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hello: hello.c hello.h
gcc -o hello hello.c
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All the example shown above gives the same result as shown below except the printout of 'make' command
Simplest makefile with Macro
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hello.c
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hello.h
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#include "hello.h"
int main(void)
{
print_hello();
return 1;
}
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#include <stdio.h>
void print_hello(void)
{
printf("Hello World \n");
}
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Example 01 >
| makefile |
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CC=gcc
hello:
$(CC) hello.c -o hello
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Example 02 >
| makefile |
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CC=gcc
hello:
$(CC) hello.c -o $@ # $@ represents 'target' ('hello' in this case)
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Example 04 >
| makefile |
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CC=gcc
hello: hello.c hello.h
$(CC) $< -o $@ # $< represents the first items of the rule ('hello.c' in this case)
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Example 05 >
| makefile |
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CC=gcc
hello: hello.c hello.h
$(CC) $^ -o $@ # $^ represents the all items of the rule ('hello.c hello.h' in this case)
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Example 06 >
| makefile |
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CC=gcc
hello: hello.c hello.h
$(CC) -o $@ $^
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All the example shown above gives the same result as shown below except the printout of 'make' command
Special Symbols
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Symbol
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Description
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$@
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file name indicating target |
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$%
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The target member name, when the target is an archive member
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$<
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The filename of the first prerequisite.
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$?
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The names of all the prerequisites that are newer than the target, with spaces between them
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$^
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The names of all the prerequisites, with spaces between them
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$+
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This is like ‘$^’, but prerequisites listed more than once are duplicated in the order they were listed in the makefile. This is primarily useful for use in linking commands where it is meaningful to repeat library file names in a particular order
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$*
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The stem with which an implicit rule matches (see How Patterns Match). If the target is dir/a.foo.b and the target pattern is a.%.b then the stem is dir/foo. The stem is useful for constructing names of related files.
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Example 01 >
| makefile |
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hello.o: hello.c hello.h # hello.o is target, [hello.c hello.h] is prerequisite
gcc -c $< -o $@ # $@ indicates the target (hello.o in this case)
# $< indicates the first elements of the prerequisites (hello.c in this case)
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Reference :
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