Digital encoding decides what the voltage on the wire, or the light in the fibre, actually does while one bit goes past. The bit values are the same either way, and the waveform carrying them is not. That choice is what this page is about.

Followings are some of the digital encoding techniquest commonly used in the field.  You would often come across these words when you are reading specification sheet or technical documents about digital communication system.

• RZ vs NRZ
• Manchester / Differential Manchester
• Bipolar AMI (Alternative Mark Inversion)
• B8ZS
• Two more members of the AMI family
• Bit stuffing, the alternative to a code table
• 4B/5B and MLT-3
• 3B/4B
• 5B/6B
• 8B/10B
• 64B/66B
• Carrying more than one bit per symbol
• Choosing between the schemes
• References :

Why we need Digital Encoding ?

A scheme that maps 1 to one voltage and 0 to another already works, so the reason for anything more elaborate is not obvious. Four problems push designers away from the simple mapping, and each of the headings below names one of them.

First I assume that you know what Encoding is (Refer to Encoding page if you are not familiar with the concept of Encoding).

Now the question is why we need Digital Encoding. Here goes some of the reason why.

Spectral Efficiency

According to Fourier Transform, a Digital Pulse contains frequencies of infinite range. So theoretically we need to implement a physical medium that can transfer the signal with infinite frequency range, but it is practically impossible. So it would be good if we can have a some technique to concentrate the frequency of digital signal into a specific region as narrow as possible. Channel Coding can be a measure to achieve this goal.

Removing DC Offset

If we just map the digital bit 1 to +V volt and bit 0 to +0 volt (or -V volt), a certain bit pattern (all zero bit or all one bit) can create DC Offset along the communication media which may cause various problem. By applying a proper Digital Encoding technique, you can reduce (even though you may not completely remove) the DC offset.

Assisting Synchronization

A certain signal pattern which does not have much transition in it (e.g, long period of '+V' or long period of '-V') may make it difficult for the reciever to get synchronized. By applying a proper encoding technique, you can reduce such a period in which the signal stays at the same voltage level. It helps synchronization on reciever side.

Increase immunitity against Signal Interference and Noise

Noise decides the error rate, and the shape of the waveform decides how far apart the receiver's decisions sit. A scheme that puts more distance between the levels it has to tell apart survives more noise before the first bit comes out wrong.

Some Coding Technique can shows the better performance in terms of BER vs SNR.

RZ vs NRZ

RZ stands for 'Return to Zero' and NRZ stands for 'No Return to Zero'. As shown in the following illustration, in RZ there is a certain period in which the signal level goes to 'zero' and stays there for some time. In NRZ, the signal jump between +V and -V at the bit boundary and never stays at zero within the bit duration.

There a couple of different type of NRZ. In concept, you can map the bit to +V or to -V in any way. The illustration shown below shows the case where '1' maps to '+V' and '0' maps to '-V'.

• The row of pink boxes along the top is the bit sequence, 0 1 0 0 1 1 0 0 0 1 1, and both traces below carry that same sequence.
• In the RZ trace a 1 rises to +V and a 0 drops to -V, and both come back to the 0 line before the bit boundary. The orange note names that return.
• In the NRZ trace the level holds for the whole bit period. Consecutive equal bits therefore merge into one flat stretch with no edge in it.
• The green verticals mark the bit boundaries, so one RZ pulse is visibly narrower than one bit period and one NRZ level is exactly as wide as it.

That narrower pulse is what RZ costs. A pulse half the width of a bit needs roughly twice the bandwidth, so RZ spends double what NRZ spends to send the same bit rate.

The spending gives an edge inside every bit. A receiver can recover its clock from those edges, and the section on Manchester further down reaches the same result by a different route.

In practice, special type of NRZ valled 'NRZ-L' and 'NRZ-I' are more frequency used. In NRZ-L, the bit '0' maps to electric level '+V' and the bit '1' maps to the electric level '-V' as shown below. In NRZ-I, the bit value does not map to any specific signal level, the bits are mapped to a certain transistion of signal level. '1' maps to 'transition' and '0' maps to 'no transision'. When it hits '0, the signal level stay same as the signal level of previous bit whatever it is. When it hits '1', the signal level changes to opposite value from the signal level of previous bit. (It may be a little bit confusing at the beginning, so try to understand the concept clearly)

• Three traces share one bit row here. The top one is RZ again, and the two below it are NRZ-L and NRZ-I.
• NRZ-L maps the value straight to a level. A 0 sits at +V and a 1 sits at -V, so the level alone says what the bit is.
• NRZ-I maps the change instead. The trace flips level at every 1 and holds through every 0, which the orange arrows across the lower trace mark bit by bit.

One consequence of that difference is worth knowing before wiring anything. NRZ-I survives a swapped pair of wires, because only the changes carry meaning and a change is still a change when both levels invert. NRZ-L does not, and every bit comes out wrong.

Their weaknesses differ as well. NRZ-L loses its clock on a long run of either value, while NRZ-I only loses it on a long run of 0, because a run of 1 keeps producing transitions.

In case of electrical signal, we can map plus(+) and minus (-) level signal to the bit '1' or '0', but in case of optical signal, we cannot do the same thing since there is no minus (-) level in optics. so one of the optical bits should be mapped to zero as shown below.

• The level labels have changed. Only +L and 0 appear, because light is either present or absent and nothing below zero exists.
• The RZ trace turns the light on for part of each 1 bit and off again before the boundary, and leaves the 0 bits dark for the whole period.
• The NRZ trace holds the light on for the whole of each 1 bit, so consecutive 1 bits merge into one long lit stretch.

An optical link is unbalanced by construction, because one bit value maps to no light at all. A run of 0 sends no energy, a run of 1 sends full power, and the average optical power moves with the data.

That is one of the reasons the block codes at the bottom of this page exist. They give the transmitter a way to keep the count of ones and zeros level without asking the physical layer for a third state it does not have.

Pros and Cons of NRZ

Everything above says what NRZ does. The two lists below weigh it, and the second one is worth reading closely. Every scheme in the rest of this page exists to fix one of the entries in it.

Pros :

• As you may recognize in the description above, it is very simple to understand and simple to implement
• Relatively good spectral efficiency : it can achieve 2 bits/Hz spectral efficiency

Cons :

• A certain bit pattern can cause DC offset. For example, '11111...' or '00000...' can cause DC offset in NRZ-L and '0000...' in NRZ-I can cause DC offset.
• Due to the same reason as DC offset, the long duration can generate a long duration of signal without any transition and this would make the reciever to get synchronized.

Manchester / Differential Manchester

In Manchester and Differential Manchester, both 0 and 1 is mapped to a certain pattern of transition. So whatever the bit pattern, you would always see the transition. The transition pattern is defined as follows :

Manchester :

• 0 => Transition from high to low in the middle of bit period
• 1 => Transition from low to high in the middle of bit period

Differential Manchester :

• 0 => Transition at the beginning of the bit period
• 1 => no transition at the beginning of the bit period
• In any case, transition happens in the middle of bit period

• Three traces share the bit row. NRZ (Electric) sits on top for comparison, Manchester in the middle, and Differential Manchester at the bottom.
• The Manchester trace carries one transition in the middle of every bit period. A 0 falls from high to low there and a 1 rises from low to high.
• The Differential Manchester trace carries a mid-bit transition in every bit as well, and adds one at the bit boundary whenever the bit is 0.
• The two orange notes state that boundary rule from the other side. A 1 extends the previous level across the boundary, and a 0 makes a transition there.

The guaranteed mid-bit transition is the reason to choose the scheme. A receiver recovers its clock from the data itself, so no separate clock line is needed and no run of identical bits can starve it.

DC balance follows from the same shape. Every bit period holds equal time high and low, so the average is zero whatever the data does, and the signal passes through transformers and AC coupled inputs without drifting.

The price is bandwidth, and it is the same price RZ pays. Every bit carries at least one transition, so the signalling rate is twice the bit rate. 10BASE-T Ethernet accepted that and 100BASE-TX did not, because 200 Mbaud on copper cost more than the simplicity was worth.

One warning belongs with the mapping above. Two opposite conventions are in use, and the rule on this page, 0 as high to low, is the IEEE 802.3 one. The other convention, usually attributed to G. E. Thomas, is its exact mirror, and a capture decoded against the wrong one inverts every bit.

Differential Manchester avoids that argument entirely. It encodes by whether a boundary transition is present rather than by which way the middle one goes, so it survives inverted wiring the way NRZ-I does. Token Ring used it for that reason.

Bipolar AMI (Alternative Mark Inversion)

Both schemes above keep the signal away from zero. This one does the opposite and uses zero as a level in its own right, which gives something neither of them can offer.

This encoding method is using 3 signal levels (+V, 0, -V). and mapping goes as follows :

• 0 => No signal. Signal level Zero
• 1 => maps the +V or -V depending on previous '1' signal. If previous '1' level is '-V', the current '1' maps to '+V', If previous '1' level is '+V', the current '1' maps to '-V'

• One trace sits under the usual bit row. Every 0 holds the line at the 0 level, which the note at the top states directly.
• Every 1 produces a pulse, and consecutive pulses alternate. The first 1 goes to +V, the next to -V, and so on down the sequence.
• The lower note gives the rule that produces the alternation : when it hits a 1, make a transition to the opposite signal level to the previous 1.
• Each pulse occupies part of the bit period rather than all of it, so AMI is a return to zero scheme as well as a three level one.

The name is older than the technique. Mark is telegraphy's word for a 1 and space for a 0, so alternate mark inversion says nothing more than flip the polarity of every 1.

The alternation is what removes the DC. Any stretch of the signal holds as many positive pulses as negative ones, to within a single pulse, so the average sits at zero and the spectrum has a null there. Transformers and AC coupled repeaters pass it without trouble.

Error detection follows from the same rule. The alternation is a rule the data cannot break, so two pulses of the same polarity in a row mean something went wrong on the line. The receiver gets that check without spending a single bit on it.

One weakness is left, and the section below fixes it. A long run of 0 holds the line at the zero level with no pulse anywhere in it, and the receiver's clock drifts.

Pros :

• Good condition for Sync in case of long string of '1's since it always make transision.
• Zero DC offset whatever the bit string is
• Bandwidth efficiency (Majority of power concentrates in less bandwith than in NRZ case)
• Possible Error Detection (If you see the same non-zero signal level more than 1 consecutive bit period, it implies there is error)

Cons :

• Possible Synchronization issue with long string of '0' since there is no transition and signal level stays always at '0'
• A little bit of redundancy because 3 levels are used to implement one bit.
• 3dB SNR loss in terms of BER vs SNR comparing to NRZ case.

B8ZS

The run of zeros that ends the section above is the problem B8ZS solves. The name states the method rather than the goal : bipolar with eight zero substitution.

The rule is short. Whenever eight zeros appear in a row, the transmitter replaces them with a fixed eight bit pattern that contains pulses, and the receiver recognises that pattern and puts the eight zeros back. The clock has something to lock to in the meantime.

That raises the question the whole scheme turns on. The receiver has to tell a substituted pattern from eight bits of ordinary data, and the substitution answers it by breaking a rule that ordinary data can never break.

Two of the pulses in the pattern take the same polarity as the pulse before them. Bipolar AMI forbids that, so a receiver seeing it knows the pulses were inserted rather than sent. The pattern is written 000VB0VB, where V is a pulse that violates the alternation and B is one that obeys it.

• The bit row reads 1 1 followed by eight 0 bits and a closing 1. Two traces carry it, plain Bipolar AMI on top and B8ZS below.
• In the upper trace the eight zeros produce one long flat stretch at the 0 level. The bracket and the green arrow mark that stretch as the thing being replaced.
• The lower trace carries the replacement. Its own labels read 0 0 0 V 1 0 V 1, and the two V positions are drawn in a different colour from the rest of the trace.
• The note at the bottom gives the identifying rule : the polarity of a V bit is always the same as the polarity of the previous 1, which is exactly what Bipolar AMI forbids.
• The note at the right points at the two bits labelled 1 and says the normal polarity rule applies to them.

The polarities in the drawing follow from the pulse before the run. That pulse sits at -V, so the substitution runs -V, +V, 0, +V, -V across the five marked positions. Each V repeats the polarity of the pulse before it and each B alternates away from it.

Counting those five tells you the balance is safe. The pattern holds two positive pulses and two negative ones, so the substitution adds nothing to the running average and the DC null of AMI survives it.

B8ZS is the line code on T1 and DS1 links in North America. The European E1 hierarchy uses HDB3 for the same job, which substitutes on runs of four zeros rather than eight and uses the same violation trick to mark what it did.

Every scheme above this one maps the data and then leaves it alone. B8ZS alters the data to protect the clock and undoes the alteration at the far end, and the block codes below do the same thing more systematically.

Two more members of the AMI family

AMI and B8ZS are not the only codes built on alternating pulses. Two relatives appear often enough to be worth naming, and one of them is what Europe uses where North America uses B8ZS.

The first is pseudoternary, which is AMI with the two bit values exchanged. A 1 holds the line at zero and a 0 produces an alternating pulse. Everything AMI offers carries over untouched, because the alternation does not care which bit value triggers it.

What the swap moves is the weakness. AMI loses its clock on a long run of 0 and pseudoternary loses it on a long run of 1. The choice between them therefore depends on which value the traffic produces less often. The ISDN basic rate S/T interface uses pseudoternary.

The second relative is HDB3, and it does the B8ZS job on a shorter run. High density bipolar 3 permits at most three consecutive zeros and substitutes on the fourth. E1 links at 2.048 Mbit/s use it, under ITU-T G.703.

Four bits leave less room than eight, so the substitution has to be cleverer. Two patterns are available rather than one, written 000V and B00V, and the encoder chooses between them on every substitution.

The choice is what protects the balance. A 000V pattern adds one pulse of a fixed polarity, so a run of them would pull the average away from zero. The encoder counts the pulses sent since the last violation and picks B00V when that count is even, which keeps the violations alternating in polarity.

The letters mean what they meant in the section above. V is a pulse that breaks the alternation and B is one that obeys it. A receiver that sees a violation therefore knows the bits around it were substituted rather than sent.

One question is worth answering before moving on. Two schemes exist for one problem because the two digital hierarchies were specified separately and by different bodies. A pair of standards solving one thing in two ways rarely has a deeper reason than that.

Bit stuffing, the alternative to a code table

Every scheme from B8ZS onward changes the data to keep transitions coming. A second way of doing that needs no table at all, and it belongs on this page alongside the codes even though it is not a code.

The rule fits in one sentence. Watch the outgoing bits, and whenever a forbidden run appears, insert one extra bit of the opposite value. The receiver applies the same rule in reverse and discards any bit that follows such a run.

HDLC is the usual example. A 0 goes in after five consecutive 1 bits, which leaves the flag sequence 01111110 unique. Six 1 bits in a row can then only be a flag and never data.

USB uses the same idea for the clock rather than for framing. The line code is NRZI, so a run of 1 is what produces no transition, and a 0 is stuffed after six consecutive 1 bits to force an edge. CAN stuffs a bit of opposite polarity after five identical ones.

The difference from a block code shows up in the overhead. Stuffing costs nothing on a stream that never reaches the run limit, and about one bit in six on a stream that reaches it constantly. The cost therefore moves with the data. A block code charges the same percentage whatever arrives.

That variability is why the fast links at the bottom of this page do not use it. A fixed line rate is easier to build a clock around, and a rate that changes with the data complicates every buffer along the path.

One limit is worth stating plainly. Bit stuffing breaks up runs and does nothing else, so it does not change the DC balance at all. A link that needs balance has to find it somewhere else.

4B/5B and MLT-3

The first block code most people meet is none of the three below. 100 Mbit/s Ethernet and FDDI both use a simpler pair, and that pair is worth following, because its two halves solve two different problems.

4B/5B maps four data bits onto five code bits. Sixteen of the thirty two available five bit words carry data, and a run length rule picks them rather than a balance rule. Each word holds at most one leading zero and at most two trailing zeros.

That rule guarantees something about the joins. However the code words land next to each other, no more than three zeros can appear in a row. The receiver's clock therefore never waits longer than three bit periods for an edge.

What the rule does not guarantee is DC balance. Nothing in 4B/5B counts ones against zeros, which makes it a run length code rather than a balanced one, and that is exactly the difference from the three sections below.

The sixteen spare words are not wasted. Some carry control rather than data, with 11111 as the idle pattern and pairs such as J and K marking the start of a frame. The remainder are invalid, so receiving one is itself an error indication.

Overhead is a quarter, so 100 Mbit/s of data leaves the encoder as 125 Mbaud. Putting 125 Mbaud on twisted pair is the problem MLT-3 was added to solve.

MLT-3 uses three levels, -1, 0 and +1, and walks a cycle through them : 0, +1, 0, -1 and back to the start. A 1 advances one step around that cycle and a 0 stays where it is.

Frequency is the whole reason for the cycle. Four consecutive 1 bits are needed to complete one full period, so the fastest waveform MLT-3 can produce has a fundamental at a quarter of the baud rate. 125 Mbaud becomes 31.25 MHz, which Category 5 cable passes comfortably.

100BASE-TX adds a third mechanism on top of those two. It scrambles the stream before MLT-3, which spreads the energy across the band and keeps the emissions down, and it is the same idea 64B/66B uses further down this page.

The division of labour is the part worth remembering. 4B/5B guarantees the transitions, MLT-3 lowers the frequency, and the scrambler spreads the spectrum. Three problems, three mechanisms, stacked rather than merged.

3B/4B Encoding

3B/4B Encoding is a method to replace '3 bit' original data (input) with '4 bit' data (output). The input and output mapping of this encoding is based on following table. (Auctually this table just shows the result of the encoding, but in many case real implementation is done by statemachine running a predefined rule).

The third column needs a word of explanation, because four of its rows offer a choice rather than an answer. Inputs 0, 3, 4 and 7 each list more than one output, and the encoder has to pick.

What decides the pick is a running count. The encoder tracks how many ones it has sent against how many zeros, a quantity called the running disparity, and chooses whichever available code word pushes that count back towards zero.

Look at which rows carry a choice and the pattern appears. Inputs 1, 2, 5 and 6 map to code words holding two ones and two zeros, which are balanced already and need no alternative. Inputs 0 and 4 map to a pair that are bitwise complements, one heavy in ones and one heavy in zeros.

Row 7 lists four options, so disparity alone does not explain it, and the selection rule there belongs to whichever standard is using the code. Treat this table as a worked illustration rather than as a specification, exactly as the paragraph above it says.

The mechanism produces the DC balance that Bipolar AMI got from a third voltage level. Here two levels are enough, because the balancing happens in the choice of code word rather than in the choice of voltage.

The cost is bandwidth again. Four bits leave the encoder for every three that enter it, so the line runs a third faster than the data, and that overhead is the price of the balance.

5B/6B Encoding

5B/6B Encoding is a method to replace '5 bit' original data (input) with '6 bit' data (output). The input and output mapping of this encoding is based on following table. (Auctually this table just shows the result of the encoding, but in many case real implementation is done by statemachine running a predefined rule).

The same choice appears in this table and follows the same rule, and the larger table makes the pattern easier to count. Eighteen of the thirty two rows carry a single code word, and the other fourteen carry a pair.

Check any of those eighteen and the reason is visible. Each holds three ones and three zeros, so it is already balanced and sending it moves the running disparity nowhere. A second version would have nothing to correct.

The fourteen pairs are bitwise complements of each other. One member carries four ones and two zeros, the other carries two ones and four zeros, and the encoder sends whichever one the running disparity currently asks for.

Overhead here is lighter than in the 3B/4B table. Six bits carry five, so the line runs 20 percent faster than the data rather than a third faster, and the section below explains why both tables exist side by side.

8B/10B Encoding

8B/10B Encoding is a method to replace '8 bit' original data (input) with '10 bit' data (output). This encoding is implemented by combining two simpler encoding method 3B/4B and 5B/6B as illustrated below.

• The label at the top is Dx.y, which is how a data code word is named in this scheme.
• The eight input bits split into two groups. The three most significant, H G F, go into the purple block, and the five least significant, E D C B A, go into the green block.
• The crossing arrows show the order changing. The green five bit group becomes the six bit group a b c d e i, and it comes first in the output. The purple three bit group becomes the four bit group f g h j, and it comes second.
• The note at the left states the arithmetic : 8B is 3B plus 5B, and 10B is 6B plus 4B.

Nothing new is defined here, and that is deliberate. 8B/10B is the 5B/6B table and the 3B/4B table above it, applied to two halves of one byte, with the six bit result placed first.

One detail decides whether the result stays balanced. The two halves share a single running disparity rather than tracking one each, so the 3B/4B encoder begins from whatever the 5B/6B encoder left behind. The stream balances as a whole rather than half by half.

Describing this in written form, it goes as follows.

i) Take the Input Data Bits: HGFEDCBA

ii) Split the Data into two blocks: HGF EDCBA

iii) Swap the position of the two blocks/shuffle the bits in each block : abcdei fghj

8B/10B is a kind of encoding scheme and it is not the predefined encoding table. The output of 8B/10B would vary depending on how the shuffling statemachine is defined. So you would need to refer to the specification of each application if you want to know exact mapping table for any specific application.

The overhead follows from the name. Ten bits go on the wire for every eight of data, so the line rate is 25 percent above the data rate. Gigabit Ethernet over 1000BASE-X therefore signals at 1.25 GHz to carry 1 Gbit/s.

The Dx.y naming points at something the tables above do not show. Alongside the data code words the scheme defines K code words, which no data byte maps to, and those carry frame delimiters and idle. Some of them hold a comma sequence that appears nowhere else, which lets a receiver find the byte boundary in a raw stream of bits.

The scheme is widely deployed rather than a curiosity. Gigabit Ethernet, PCI Express generations 1 and 2, SATA, USB 3.0, DisplayPort and Fibre Channel all run on it, and the section below explains what replaced it as rates rose.

64B/66B Encoding

64B/66B encoding convert a 64 bit input block into 66 output block using a complicated scrambling algorithm (not a fixed mapping table). The structure of the output block varies in many different structure and the type of the structure is indicated by the two sync bits at the beginning of the output block as shown below. This econding method is mainly used for 10 Gbit Ethernet (if you are interested in further details, refer to the documents in Reference section).

• The blue bar at the top is the 64 bit input block, and the pale green arrows carry it downward through the flow.
• The orange box is the scrambler, and it carries its polynomial, X⁵⁸ + X³⁹ + 1.
• The purple bar is the output. It is the 64 bit payload block with a two bit sync field, drawn in red, placed in front of it.
• The list at the bottom gives the four values of that field. 01 means the 64 bits are all data, 10 means they mix data and control, and 00 and 11 are code errors.

Look at which two values are legal and the reason appears. 01 and 10 both contain a transition and 00 and 11 do not, so a legal header guarantees one edge every 66 bits whatever the scrambler produced. The receiver looks for that regular edge to find the block boundary.

Scrambling replaces the table for a plain reason of size. A lookup table for a 64 bit input would need 2⁶⁴ entries, so the scrambler mixes the data with a pseudo-random sequence instead.

That swap changes what the code promises. 8B/10B guarantees balance, while 64B/66B only makes a long run of identical bits improbable. Nothing forbids a payload that scrambles into something awkward, and the design accepts that risk.

What it saves is overhead. Two bits per 64 is about 3 percent, against 25 percent for 8B/10B, and at 10 Gbit/s that difference is worth more than a guarantee. 10GBASE-R uses it, the same idea carries into 40G and 100G, and PCI Express moved to 128B/130B at generation 3 for the same reason.

The scrambler is self synchronising, so the two ends need no shared starting state. Once the sync headers line up, the descrambler locks from the data itself and stays locked.

Carrying more than one bit per symbol

Every scheme so far sends one bit per symbol, and several of them send less. Raising that ratio is the other way to move more data through a given bandwidth, and it is where the fastest links now spend their effort.

The idea needs no encoding table. A symbol with four distinguishable levels carries two bits and one with eight carries three, so the symbol rate stays where it was while the bit rate multiplies.

Noise margin pays for it. Four levels split the same voltage range, so each decision has a third of the room it had with two. Holding the same error rate then costs roughly 9.5 dB of signal to noise ratio.

2B1Q is the oldest of these still in service. Two bits map to one quaternary symbol at levels -3, -1, +1 and +3, so 160 kbit/s becomes 80 kbaud. The ISDN basic rate U interface and HDSL both run on it.

1000BASE-T pushes the same idea much further. It uses five levels on each of four pairs at once, and every pair carries 125 Mbaud in both directions. Two bits per symbol per pair therefore gives 250 Mbit/s per pair and 1 Gbit/s in total.

The fifth level carries no data. It supplies the redundancy the trellis code needs to correct errors, which is the first appearance on this page of a line code and an error correcting code designed together.

PAM4 is the current answer at the top of the range. Four levels carry two bits per symbol, and 200G and 400G Ethernet use it, as does PCI Express from generation 6 onward.

PAM4 is never used on its own. The 9.5 dB it costs is more than a modern link can spare, so forward error correction runs beside it as standard, usually Reed-Solomon.

One pattern runs the length of this page. At low rates the effort goes into the shape of each bit, and at high rates it goes into packing bits into symbols and then repairing what the noise does. The codes at the top never needed a repair layer, and the ones at the bottom cannot work without one.

Choosing between the schemes

The schemes above answer the four problems at the top of this page in different proportions. The table below puts them side by side so the trades are visible in one place.

Read the cost column against the DC balance column in particular. Almost every scheme on the page pays for balance or clock recovery with bandwidth, and the differences are mostly about how much.

The table falls into four groups, and they arrived in that order historically. The first encodes a bit as a level, the second encodes it as a transition, the third replaces blocks of bits with longer blocks chosen for their shape, and the fourth puts several bits into one symbol.

Moving down the table, the guarantee weakens and the overhead falls. Manchester balances every single bit and pays 100 percent. 8B/10B balances over a byte and pays 25 percent. 64B/66B only makes imbalance unlikely and pays 3 percent.

Rate is what drives that trend. At 10 Mbit/s a doubling of bandwidth costs almost nothing, and at 10 Gbit/s it costs more than any receiver design saves. Higher rates therefore take their clock recovery in the cheapest way that still works.

One practical note closes the comparison. These schemes detect an error at best, and none of them corrects one. Error correction is a separate layer, and the Coding page covers the codes that do that job.

References :

[1] 8B/10B Coding,64B/66B Coding  

[2] 64b/66b line code

[3] Introduction to 10 Gigabit 64b/66b (Clause 49)

[4] 10G ETHERNET 64B/66B ENCODING