Descriptions will follow later.. enjoy illustrations and screen capture and try to make some story about it on your own for now. The text added below each illustration now gives a first version of that story, with the numbers checked against 25.221.

TD-SCDMA is the 1.28 Mcps option of UTRA TDD. The uplink and the downlink share one carrier and take turns in time, so the frame has to say which slot goes in which direction and where the direction changes. This page builds the full picture in steps. It starts with the time, code and frequency view, then the frame in time and the burst inside a slot. It ends with real bursts on a spectrum analyzer during call processing.

• Frame Structure - Time, OVSF, Frequency Domain
• Frame Structure - Time Domain
• Slot Structure - Burst Format - 1.28 Mcps
• Snapshot on Spectrum Analyzer
• Frame/Burst in Call Processing
• UpPTS, RACH
• DwPTS
• Slot 0, DwPTS
• Slot 0, DwPTS, Slot 4
• Slot 4 - DL, Slot 1 - UL
• DwPTS, Slot 1 - UL
• Slot 0, DwPTS, Slot 1
• CCPCH, PICH, D-DPCH
• Reference

Frame Structure - Time, OVSF, Frequency Domain

A TD-SCDMA cell divides its radio resource in three dimensions at once: time slots, OVSF codes and carriers. Before we look at any single burst, it helps to see all three together, because every channel on this page occupies one cell of that grid.

The diagram below draws one 5 ms subframe as a block. Time runs to the right through TS0, DwPTS, GP, UpPTS and TS1 to TS6. The vertical axis is power density, and the depth of each slot holds the OVSF codes 0 to 15. Carrier 2 and Carrier 3 stand behind Carrier 1 with the same structure, 1.6 MHz apart. The two red Switch Point labels mark where the direction changes.

One carrier offers 7 traffic slots with up to 16 codes each, and each extra carrier adds the same grid. The switch points decide how the slots are split between downlink and uplink.

• TS0 is DL and TS1 is UL. In this drawing TS1 to TS3 are UL and TS4 to TS6 are DL.
• The first switch point, from DL to UL, is inside the special period of DwPTS, GP and UpPTS. The second one, from UL to DL, is between TS3 and TS4.
• Each slot can carry up to 16 channelisation codes, the number of codes at SF 16.
• The red box around TS6 points out that the data layout inside a slot is its slot format, which 25.221 defines.

The 1.6 MHz spacing is the nominal channel spacing of the 1.28 Mcps TDD option in 25.102. A cell may use several carriers, and 25.221 subclause 5A.3.1 then calls the carrier with the P-CCPCH the primary frequency. The others are secondary frequencies. The S-CCPCH, the PICH and the PRACH are sent only on the primary frequency.

• A resource unit is a slot, a code and a carrier : every physical channel is placed by these three values.
• The switch points set the DL/UL ratio : only TS0 and TS1 have a fixed direction.
• Common channels stay on the primary frequency : secondary carriers add capacity for traffic.

Frame Structure - Time Domain

The time structure decides everything else on this page. Once you know the lengths of the slots and of the special fields, you can place any channel in time and find it again on an analyzer.

Following is the overall frame structure for 1.28 Mcps options. For other option (e.g, 3.84, 7.68 Mcps), refer to 25.221 5.1 and 5B.1). The details for this section is based on 25.221 5A.1.

Just read following figure and try to verbalize it, you can figure out a lot of details just by "READING" the figure. If I do a little bit of list for you, it would be as follows. (Some items in this list cannot be read from the figure. They are specified in specification)

• one radio frame is 10 ms length
• one radio frame is made up of 2 subframes and each of these subframes has 5 ms length
• the two subframe structure within a radio frame has same structure.
• each subframe has 7 time slots in it
• length of each time slot is 864 chips in length
• among the 7 traffic time slots, time slot#0 is always allocated as downlink and time slot#1 is always allocated as uplink.
• there must be at least one downlink slot and at least one uplink slot within a subframe. As long as this requirement is met, you can create any combination of uplink and downlink slots.
• In a multi-frequency cell, the traffic time slots allocated for uplink and downlink pair(s) for one UE should be on the same carrier.
• In a multi-frequency cell, it is suggested the switching point configuration on secondary frequencies to be the same as that on primary frequency.

Seven 864-chip slots and the 352 chips of DwPTS, GP and UpPTS fill each 6400-chip subframe exactly.

Let's check the numbers in the diagram, because they all add up. At 1.28 Mcps, 864 chips last 675 microseconds, 96 chips last 75 microseconds and 160 chips last 125 microseconds. One subframe holds 7 x 864 + 96 + 96 + 160 = 6400 chips, which is exactly 5 ms. Two subframes make the 10 ms frame.

The special period has its own inner structure. The DwPTS is 32 chips of GP and 64 chips of SYNC-DL. The UpPTS is 128 chips of SYNC-UL and 32 chips of GP. 25.223 defines the two codes. The SYNC-DL code has 64 chips and the SYNC-UL code has 128 chips, and neither code is scrambled.

The lower right of the diagram opens one traffic slot. It holds two data fields of 352 chips, a midamble of 144 chips and a guard period of 16 chips, as in 25.221 subclause 5A.2.2. The table beside it is 25.221 Table 8A. The number of symbols per data field is 352 divided by the spreading factor, so SF 16 gives 22 symbols and SF 1 gives 352 symbols.

• Everything is a multiple of the chip time : at 1.28 Mcps one chip is 0.78125 microseconds, so 864 chips are 675 microseconds.
• The special period sits between TS0 and TS1 : DwPTS, GP and UpPTS take 352 chips and give the first DL to UL switch point.
• The midamble is in the middle of every burst : the receiver estimates the channel from it for both data fields.

Slot Structure - Burst Format - 1.28 Mcps

Every channel of the 1.28 Mcps option uses the same traffic burst, so one slot structure covers almost all of them. The channels differ in which optional fields the burst carries: TFCI, SS and TPC. So we start with the DPCH, which can carry all three, and then compare each common channel with it.

Dedicated Physical Channel : DPCH

The DPCH shows the burst with every optional field. The two diagrams below place the TFCI, SS and TPC symbols around the midamble. The upper diagram has TFCI only, and the lower one adds SS and TPC.

In the upper diagram, the TFCI code word is split into four parts. The 1st and 2nd parts sit on both sides of the midamble in the first subframe, and the 3rd and 4th parts do the same in the second subframe. Each slot is 864 chips long.

The TFCI code word is spread over both subframes of a radio frame, directly next to the midamble.

In the lower diagram, the SS symbol and the TPC symbol follow the midamble, and the 2nd or 4th part of the TFCI comes after them. The right half of the lower diagram is labelled as the first subframe again, but its TFCI parts 3 and 4 show that it is the second subframe.

With SS and TPC present, the order after the midamble is SS, TPC and then the TFCI part.

• 25.221 subclause 5A.2.2.1 distributes the TFCI code word bits equally between the two subframes and the two data fields.
• The TFCI is always present in the first timeslot of a radio frame for each CCTrCH, on the physical channel with the lowest physical channel sequence number.
• The TPC is sent at least once per 5 ms subframe, directly after the SS, which follows the midamble.
• The SS commands a timing adjustment of k/8 chip every M subframes, where the network sets k and M from 1 to 8.

Primary common control physical channel : P-CCPCH

Same as DPCH burst format except that no TFCI is applied. 25.221 subclause 5A.3.1 fixes its position, so no signalling is needed to find it. P-CCPCH1 and P-CCPCH2 use the first two code channels of time slot 0 with SF 16. The phase of the SYNC-DL in DwPTS tells the UE where the P-CCPCH interleaving period starts.

Secondary common control physical channel : S-CCPCH

Same as DPCH burst format and TFCI may apply as well. It carries the PCH and the FACH with SF 16. Its time slot and codes are broadcast on the BCH, and in a multi-frequency cell it is sent only on the primary frequency.

Fast Physical Access CHannel : FPACH

Same as DPCH burst format. The FPACH uses one SF 16 code, so its burst has 2 x 22 = 44 symbols. The Node B sends it to acknowledge a detected SYNC-UL signature. Its 32 information bits carry the signature reference number, the relative sub-frame number, the received starting position of the UpPCH and the transmit power level command for the RACH message.

physical random access channel : PRACH

Same as DPCH burst format. The PRACH uses SF 16, SF 8 or SF 4, and the allowed codes are broadcast on the BCH. The UE sends it only after the FPACH has acknowledged its SYNC-UL code, so the PRACH burst arrives with the timing and power that the FPACH gave.

High Speed Physical Downlink Shared Channel : HS-PDSCH

Same as DPCH burst format, but be careful.. slot format for HS-PDSCH is different from PDCH slot format. 25.221 Table 8KA lists its slot formats. They carry no TFCI, no SS and no TPC, and they use SF 16 or SF 1 with QPSK, 16QAM or 64QAM.

• One burst serves all channels : two 352-chip data fields, a 144-chip midamble and a 16-chip guard period.
• Optional fields make the difference : the P-CCPCH has no TFCI, the S-CCPCH may have one, and the HS-PDSCH has no TFCI, SS or TPC.
• The P-CCPCH is the only fixed channel : all other common channel positions come from system information.

Snapshot on Spectrum Analyzer

The diagrams above are drawings of the specification. A power versus time trace shows whether a real Node B and UE follow them, and it also teaches you to recognise each part of the frame by its length.

Following is some snapshots of these frame structure being implemented in real application. I captured these subframes during real communication using vector spectrum analyzer.

The trace below covers 2 ms from 998.91 ms. The labels at the top measure three parts of it. SLOT 0 - DL lasts 675 microseconds or 864 chips, SYNC-DL lasts 50 microseconds or 64 chips, and SYNC-UL lasts 100 microseconds or 128 chips. The spectrogram under the trace shows the same bursts over a longer time.

The measured lengths of Slot 0, SYNC-DL and SYNC-UL match 864, 64 and 128 chips at 1.28 Mcps.

• Slot 0 is a block at about -65 dBm, followed by the short SYNC-DL burst of the DwPTS.
• The gap between SYNC-DL and SYNC-UL is the 96-chip GP, about 75 microseconds.
• The SYNC-UL burst is about 50 dB above the downlink at the analyzer input. This level difference shows how the analyzer was connected to the two transmitters. It does not compare their powers over the air.

The lengths are the useful part of such a trace. 64 chips at 1.28 Mcps are 50 microseconds and 128 chips are 100 microseconds, so the markers identify each burst without any decoding.

• Burst length identifies the burst : 675 microseconds is a traffic slot, 50 microseconds is SYNC-DL and 100 microseconds is SYNC-UL.
• Levels depend on the test setup : compare levels only between bursts from the same transmitter.

Frame/Burst in Call Processing

A call uses more slots as it moves from idle to random access and then to a connection. The overall trace below covers about 4.9 s of such a sequence, and the traces after it zoom into short windows to show which slots are active at each stage.

In the trace below, a short spike above +10 dBm appears near the start. After it, the level rises to about -10 dBm and stays there for most of the capture. Near the end it steps up again to about +20 dBm. The spectrogram shows the same three stages in colour.

Each rise in the averaged level marks a stage where more slots, or stronger bursts, become active.

UpPTS, RACH

Random access is the first thing the UE sends. The two traces below show the UpPTS burst that carries the SYNC-UL code, and after it the PRACH bursts of the RACH message.

The first trace covers 600 ms from 131.25 ms. The UpPTS burst reaches about -25 dBm, and the RACH bursts right after it reach about +20 dBm. Later in the window, a regular train of bursts starts and grows in level.

The SYNC-UL in UpPTS comes first, and the RACH message follows shortly after it.

The second trace covers 92 ms and zooms into the same step. The UpPTS burst is at the left. The first PRACH burst comes around 30 ms later, and a second one follows around 5 ms after that. The small bursts every 5 ms are the downlink.

About 30 ms pass between the SYNC-UL and the RACH message, and the message spans two subframes.

• 25.224 subclause 5.6.3 lets the FPACH answer up to WT subframes after the SYNC-UL, and the PRACH follows 2 subframes after the FPACH. With WT = 4, the largest value, the gap can reach 6 or 7 subframes, which is 30 to 35 ms. The gap of around 30 ms in the trace fits this rule.
• The two PRACH bursts 5 ms apart fit a RACH message that lasts 2 subframes, with one burst in each subframe.

DwPTS

The DwPTS is sent in every subframe, whatever else the cell is doing. So it is the one burst you can always find on a carrier, even before any UE is connected.

The trace below covers 54 ms. The bracket marks a row of narrow spikes at about -50 dBm, one per 5 ms subframe. Wider bursts appear at the right end of the window.

The DwPTS repeats once per 5 ms subframe at a constant level.

25.221 subclause 5A.3.5 explains why the spikes look so regular. The DwPCH is sent in every subframe with whole cell coverage and at a constant power level that higher layers signal.

Slot 0, DwPTS

Slot 0 sits directly before the DwPTS, so on the analyzer the two often look like one block with a short spike at its end. The 12 ms trace below separates them.

The DL Slot 0 block is at about -55 dBm, and the DwPTS spike follows right after it. Another downlink burst appears about 3 ms later, which is where Slot 4 falls, as the next trace shows.

Slot 0 and the DwPTS are neighbours in time, separated only by the end of the 864-chip slot.

Slot 0, DwPTS, Slot 4

This 7 ms trace adds the first downlink traffic slot that follows the uplink slots. The two markers also measure the subframe period directly, without any decoding.

Marker 1 at 339.1958 ms is on Slot 0 and Marker 2 at 344.2064 ms is on the next Slot 0, so the difference of 5.0106 ms is one subframe. DL Slot 4 starts about 3 ms after Slot 0. Nothing appears in Slots 1 to 3 here, so the UE is not sending in this window.

Slot 4 starts 3808 chips, about 2.975 ms, after the start of Slot 0.

The 3808 chips come from the frame structure: Slot 0 of 864 chips, the 352 chips of DwPTS, GP and UpPTS, and Slots 1 to 3 of 864 chips each.

Slot 4 - DL, Slot 1 - UL

Here the uplink starts. The 70 ms trace shows the downlink Slot 4 bursts at a low level, and then the UL Slot 1 bursts appear at a much higher level.

The DL Slot 4 bursts are at about -50 dBm and repeat every 5 ms. From about 470 ms, UL Slot 1 bursts appear at about -30 dBm, also once per subframe.

Once the UE transmits, UL Slot 1 appears in every subframe next to the downlink bursts.

DwPTS, Slot 1 - UL

Zooming to 10 ms shows the order inside one subframe. The DwPTS comes first, and the UL Slot 1 burst follows after the short GP and UpPTS.

The DwPTS spike is at about -50 dBm and the UL Slot 1 block at about -20 dBm. A lower burst at about -45 dBm follows around 2 ms after Slot 1 starts, which is where DL Slot 4 falls. The markers are 5.082 ms apart, about one subframe.

Only the 96-chip GP and the 160-chip UpPTS separate the DwPTS from UL Slot 1.

The 2 ms step from Slot 1 to Slot 4 is three slots of 864 chips, which is 2592 chips or 2.025 ms.

Slot 0, DwPTS, Slot 1

This trace shows the downlink Slot 0, the DwPTS and the uplink Slot 1 in one subframe. So the whole DL to UL switch point is visible in one picture.

DL Slot 0 is at about -60 dBm, the DwPTS spike follows, and UL Slot 1 rises to about +2 dBm. The two markers are exactly 5.000 ms apart, one subframe.

The first switch point of the subframe lies between the DwPTS and UL Slot 1.

CCPCH, PICH, D-DPCH

The last trace separates the downlink channels by what they carry. It marks which burst belongs to the common channels and which to the dedicated channel.

The trace covers 50 ms. The label P-CCPCH, S-CCPCH, PICH points at one burst, and the label D-DPCH points at another burst about 5 ms later, as the arrow at the top shows. The tall bursts in between are not labelled.

The common channels and the dedicated downlink channel appear as separate bursts, one subframe apart in this trace.

The trace does not show the slot numbers. On the Common Channel Configuration page, the SIB5 example puts the PICH and the S-CCPCH in Slot 0, next to the P-CCPCH.

• Random access comes first : the UpPTS burst with SYNC-UL precedes the PRACH bursts by around 30 ms.
• DwPTS and Slot 0 never stop : they appear in every subframe, with or without a call.
• Timing checks are simple arithmetic : slot offsets such as 3808 chips from Slot 0 to Slot 4 match the analyzer markers.

Reference

• 3GPP TS 25.221 v19.0.0 : Physical channels and mapping of transport channels onto physical channels (TDD), clause 5A
• 3GPP TS 25.223 v19.0.0 : Spreading and modulation (TDD), SYNC-DL and SYNC-UL
• 3GPP TS 25.224 v19.0.0 : Physical layer procedures (TDD), subclause 5.6
• 3GPP TS 25.102 v19.0.0 : User Equipment (UE) radio transmission and reception (TDD), subclause 5.4.1.2