Uplink Frame Timing

In R99 (WCDMA) case, the only Uplink channel you have is PRACH and DPDCH/DPCCH, but PRACH is special case which will be described in detail in 'RACH Process' section. Here we only think about DPDCH/DPCCH.

The uplink has no timing reference of its own. The UE takes the timing of its uplink frame from the downlink frame it receives, and then adds a fixed offset. Let's see what that offset is, why it has this value, and how precisely the UE must hold it.

Uplink DPDCH/DPCCH timing is 1024 chips after downlink DPDCH/DPCCH timing.

That one sentence is the whole rule, but each part of it hides a detail. The downlink frame here is the dedicated DPCH or the F-DPCH, not the P-CCPCH. The 1024 chips are measured at the UE antenna. In soft handover, only one of several downlinks sets the timing.

How is the uplink DPCCH/DPDCH frame placed against the downlink ?

The UE never receives an absolute clock from UTRAN. What it does receive is its downlink DPCH, or the F-DPCH when the connection has no downlink DPDCH. So the uplink frame has to be tied to something the UE can observe, and 25.211 ties it to the received downlink frame.

25.211 subclause 7.6.3 states the rule. The UE starts its uplink DPCCH/DPDCH frame approximately T₀ chips after it receives the first detected path of the corresponding downlink DPCCH/DPDCH or F-DPCH frame. T₀ is a constant of 1024 chips. At 3.84 Mcps this is about 266.7 microseconds, or 0.4 of a 2560-chip slot.

Two words in that rule matter. The word "reception" means that the offset is measured at the UE antenna, after the propagation delay. The phrase "first detected path" means the earliest multipath component that the UE finds, not the strongest one.

The downlink DPCH is not aligned to the P-CCPCH either. 25.211 subclause 7.1 shifts each DPCH by τ_DPCH,n = T_n x 256 chips, with T_n from 0 to 149. So two UEs in the same cell usually send their uplink frames at different times, because each one follows its own downlink DPCH.

The diagram below follows one frame boundary around the loop. The top row is the downlink DPCH as the Node B sends it. The UE receives it one propagation delay t_p later, waits T₀, and starts its uplink frame. The Node B receives that uplink frame another t_p later.

Figure 1. Uplink frame timing, not to scale. The UE fixes the 1024-chip gap at its own antenna, so the Node B sees the uplink frame arrive T₀ plus twice the propagation delay after it sent the downlink frame.

The Node B can use this fixed gap. 25.215 defines the Round trip time measurement as RTT = T_RX - T_TX. T_TX is the start of the downlink DPCH or F-DPCH frame at the Node B transmit antenna. T_RX is the first detected path of the corresponding uplink DPCCH frame at the receive antenna. The UE holds T₀ constant, so RTT minus 1024 chips gives twice the one-way propagation delay. One chip is about 78 m of radio path.

The uplink follows the received downlink : the UE counts T₀ from the first detected path of its own DPCH or F-DPCH frame, not from the P-CCPCH.
T₀ is a constant : it is 1024 chips, about 266.7 microseconds, and no RRC message configures it.
Each UE has its own uplink timing : the DPCH offset T_n x 256 chips differs from UE to UE, so the uplink frames of different UEs are not aligned.
RTT carries the distance : the Node B sees T₀ plus twice the propagation delay, so the RTT measurement can be turned into a UE distance.

Why is the offset 1024 chips ?

A fixed offset raises an obvious question. Why does the UE not simply transmit at the same moment it receives the downlink frame ? The answer is in the inner loop power control, which runs once per slot in both directions.

25.214 Annex B.1 gives the reason in one sentence. The uplink DPCH is delayed by 1024 chips from the downlink DPCH, measured at the UE antenna, to maximise the cell radius within which one-slot control delay is achieved. So the offset exists to make the power control loop fast.

Let's follow the downlink loop step by step. The UE measures the downlink SIR, mostly on the pilot field of the downlink DPCH. It then sends a TPC command in the uplink. For the DPCH, the uplink TPC field starts 512 chips after the end of the downlink pilot field, measured at the UE antenna. The Node B receives that TPC command and changes its DPCH power at the beginning of the next downlink pilot field.

The propagation delay sits inside this loop twice. The downlink pilot needs t_p to reach the UE, and the uplink TPC command needs t_p to come back. A larger cell therefore leaves the Node B less time to decode the command before the next pilot field. The 1024-chip value places the uplink slot so that this margin covers as large a cell as possible.

The uplink loop works the other way round. The UE changes its uplink DPCH power at the beginning of the first uplink pilot field after it receives a downlink TPC command. Annex B is informative. It explains the choice, while the binding rule stays in 25.211 subclause 7.6.3.

Other procedures depend on the same slot pairing. In closed loop transmit diversity, 25.214 describes the feedback command in uplink slot i as sent about 1024 chips after the received downlink slot j. The Node B then applies the new antenna weight at the pilot field of downlink slot (j+1) mod 15 or (j+2) mod 15. For the F-DPCH, the TPC command combining period begins 512 chips after the downlink slot boundary.

The offset serves the inner loop power control : it lets a TPC command change the transmit power one slot after the measurement.
Cell size reduces the margin : the round trip delay sits inside the loop, so 1024 chips was chosen to keep one-slot delay over the largest radius.
Other slot-based feedback uses the same pairing : closed loop transmit diversity counts its feedback delay from the same 1024-chip relation.

Which cell sets the timing in soft handover ?

With one radio link the rule is simple. In soft handover the UE receives the same DPCH from several cells, and these cells are not synchronised with each other. But the UE still sends only one uplink frame, so one cell has to be the reference.

25.133 subclause 7.1 calls this cell the reference cell. When the UE is not in soft handover, the reference cell is the one cell in its active set. When the UE starts in soft handover, the reference cell is the cell used to calculate the initial CFN. The reference cell keeps this role when other cells join the active set. If it is removed from the active set, the UE starts adjusting its transmit timing, at the latest when the whole active set update message is available.

The other radio links must fit around that uplink timing. 25.214 subclause 4.3.2.4 covers this in synchronization procedure B. UTRAN starts the downlink DPCH or F-DPCH of each new radio link so that it reaches the UE within T₀ +/- 148 chips before the uplink frame. To choose that start, UTRAN needs to know where the new cell sits in time. The UE supplies this with the SFN-CFN observed time difference of 25.215, which is measured against T_UETx - T₀, the uplink frame start minus 1024 chips.

25.133 subclause 7.2 sets the receiver side of the same window. The UE must receive, demodulate and combine a downlink DPCH or F-DPCH whose receive timing lies within T₀ +/- 148 chips before the transmit timing. The UE only has to apply a TPC command in the immediate next slot when every cell in the active set lies inside this window. Otherwise it may apply the power change one slot later.

The UE reports how each link sits in the window with the UE Rx-Tx time difference of 25.215. This is the time between the uplink DPCCH frame transmission and the first detected path of the downlink DPCH or F-DPCH frame from the measured radio link. For both type 1 and type 2, 25.133 gives a reporting range of 768 to 1280 chips, which is T₀ - 256 to T₀ + 256.

One reference cell sets the uplink timing : it is the cell used for the initial CFN, and it stays the reference until it leaves the active set.
New radio links are aligned by UTRAN : the network chooses each new DPCH frame offset so that the frame arrives within T₀ +/- 148 chips.
T₀ appears in the UE measurements : both the SFN-CFN observed time difference and the Rx-Tx time difference are defined around the 1024-chip offset.

How precisely must the UE hold the timing ?

The word "approximately" in 25.211 needs a number behind it. The UE clock drifts, and the received downlink moves as the UE moves, so 25.133 subclause 7.1 sets an initial accuracy and also rules for following the change.

The initial transmission timing error must be 1.5 chips or less. This applies to the first transmission on the DPCCH/DPDCH. The reference point is the first detected path of the downlink frame from the reference cell, plus T₀ chips. After that, the UE follows the received downlink frame. When the timing error exceeds 1.5 chips, the UE must bring it back within 1.5 chips.

Three rules limit how the UE makes that correction. The first is that one adjustment changes the timing by at most 1/4 chip, which is about 65 ns. The second is a minimum adjustment rate of 233 ns per second. The third is a maximum adjustment rate of 1/4 chip per 200 ms. 25.133 also states the maximum rate as a window. In any 800 x d ms period, the timing must not change by more than d chip, where d is between 0 and 1/4.

So the UE corrects the timing in small steps, and not in one jump. The minimum rate makes sure the UE does not fall behind a UE that moves. The maximum rate limits how fast the uplink timing moves at the Node B receiver.

One case skips the initial accuracy rule. After a timing-maintained hard handover, when higher layers tell the UE not to perform the synchronisation procedure, the UE resumes with the transmit timing it used before the handover. It does the same when it returns to the old channels after a failed hard handover. The normal adjustment rules then apply from that point.

1.5 chips is the limit : about 390 ns, both for the first transmission and before the UE must correct itself.
Corrections are slow and small : at most 1/4 chip per step and at most 1/4 chip per 200 ms.
A timing-maintained handover keeps the old timing : the UE does not rebuild T₀ from the new cell in that case.

Do the other uplink channels follow the same timing ?

The existing text of this page is about R99, but a Release 5 or later UE sends more than the DPCCH and the DPDCH. Most of the later uplink channels reuse the DPCCH frame timing. The HS-DPCCH is the exception, because it has to follow the HSDPA subframes.

25.211 puts the following channels on exactly the same frame timing as the uplink DPCCH.

E-DPCCH and E-DPDCH for HSUPA, subclause 7.13
S-DPCCH for uplink MIMO, subclause 7.14
S-E-DPCCH and S-E-DPDCH for the secondary stream, subclause 7.16
DPCCH2, subclause 7.17

The HS-DPCCH carries HARQ-ACK and CQI for the 2 ms HS-PDSCH subframes, so it cannot simply use the 10 ms DPCH frame boundary. In 25.211 subclause 7.7.1, an HS-DPCCH subframe starts m x 256 chips after the start of the uplink DPCH frame, with m = (T_{TX_diff} / 256) + 101. T_{TX_diff} is the transmit time difference between the start of the related HS-PDSCH subframe and the start of the downlink DPCH or F-DPCH frame that contains it. It takes a value from 0 to 38144 in steps of 256 chips.

We can check what this gives at the UE. The uplink DPCH frame starts T₀ = 1024 chips after the downlink DPCH frame, and 101 x 256 = 25856 chips. So the HS-DPCCH subframe starts 26880 chips after the start of the HS-PDSCH subframe. The HS-PDSCH subframe lasts 7680 chips, so the HARQ-ACK starts 19200 chips, or 7.5 slots, after the end of the HS-PDSCH subframe.

The PRACH does not use T₀ at all. 25.211 subclause 7.3 aligns the uplink access slots with the AICH access slots. Uplink access slot n is sent τ_p-a chips before the reception of downlink access slot n. τ_p-a is 7680 chips when AICH_Transmission_Timing is 0, and 12800 chips when it is 1. This is why the page treats the PRACH as a special case.

HSUPA and uplink MIMO channels copy the DPCCH timing : E-DPCCH, E-DPDCH, S-DPCCH, S-E-DPCCH, S-E-DPDCH and DPCCH2 all start with the DPCCH frame.
The HS-DPCCH follows the HS-PDSCH : its offset of m x 256 chips puts the start of the HARQ-ACK 7.5 slots after the end of the HS-PDSCH subframe.
The PRACH follows the AICH access slots : its timing uses τ_p-a, not T₀.

Reference

3GPP TS 25.211 v19.0.0 : Physical channels and mapping of transport channels onto physical channels (FDD), subclauses 7.1, 7.3, 7.6.3, 7.7.1, 7.13 to 7.17
3GPP TS 25.214 v19.0.0 : Physical layer procedures (FDD), subclause 4.3.2.4 and Annex B.1
3GPP TS 25.133 v19.0.0 : Requirements for support of radio resource management (FDD), subclauses 7.1 and 7.2
3GPP TS 25.215 v19.0.0 : Physical layer - Measurements (FDD), subclauses 5.1.8, 5.1.10 and 5.2.8